1. Technical Field
The present invention relates to a semiconductor device, and to a method of manufacturing the same.
2. Related Art
A capacitor is one of fundamental devices, and employed in a versatile manner as a decoupling condenser or a booster circuit. Essential characteristics of the capacitor include the capacitance per unit area. This is because a larger capacitance per unit area of the capacitor allows reducing the area necessary for acquiring the desired capacitance. In particular, the decoupling condenser for stabilizing a source voltage requires a large footprint, and hence increasing the capacitance per unit area of the capacitor effectively contributes to reducing the area of the chip.
FIG. 9 is a cross-sectional view of a gate capacitor, popularly utilized as the capacitor. The gate capacitor shown in FIG. 9 includes a substrate 201, an insulating layer 202 provided thereon, and a conductive layer 203 provided on the insulating layer 202.
A technique for improving the gate capacitance can be found, for example, in JP-A No. 2005-353657.
FIG. 10 depicts a structure of a semiconductor chip described in the cited literature. The device shown in FIG. 10 includes a substrate 301, an isolation region including a first trench 302a formed on the substrate and insulating layers 303, 304 buried in the first trench, and a capacitance region having a lower electrode constituted of a second trench 302b formed on the substrate except for the isolation region and a diffusion layer 305 formed on a region including the second trench 302b. In such structure, the inner portion of the second trench 302b can serve as a part of the effective area of the capacitor formed in the capacitance region. Such configuration enables significantly reducing the footprint of the capacitor on the substrate, without compromise in amount of capacitance. Consequently, a higher level of integration and chip density of the semiconductor device can be achieved.
In addition, JP-A No. 2000-332101 discloses a structure in which a trench including a single segment and a trench including a plurality of continuous segments are provided in a substrate.
JP-A No. S60-148164 discloses a structure including an isolation trench and memory capacitors provided on the respective sides thereof, in which trenches are formed in different depths in the substrate.
JP-A No. H01-119055 discloses a method of forming a capacitor, including forming a gate electrode on a sidewall of a recessed portion of a substrate, removing a gate insulating layer on a bottom portion of the recessed portion, selectively removing the substrate so as to form a recessed portion, and forming the capacitor so as to fill the recessed portion.    [Patent document 1] JP-A No. 2005-353657    [Patent document 2] JP-A No. 2000-332101    [Patent document 3] JP-A No. S60-148164    [Patent document 4] JP-A No. H01-119055
In the gate capacitor shown in FIG. 9, the surface area of the capacitance per unit area on the main surface of the substrate, in other words the capacitance per two-dimensional unit area, is unchanged once the capacitance layer thickness is uniquely determined. On the other hand, in the gate capacitor according to the patented document 1, the effective capacitance per two-dimensional unit area is increased utilizing the sidewall of the trench.
The technique according to the patented document 1, however, still has a room for improvement in that the effective area of the capacitor is to be increased with a minimal increase in number of manufacturing steps.